; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64 -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=PIC
; RUN: llc -mtriple=x86_64-windows -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=WIN

define i64 @i64_test(i64 %i) nounwind readnone {
; PIC-LABEL: i64_test:
; PIC:       SelectionDAG has 12 nodes:
; PIC-NEXT:    t0: ch,glue = EntryToken
; PIC-NEXT:    t2: i64,ch = CopyFromReg t0, Register:i64 %0
; PIC-NEXT:    t7: i64,i32,ch = ADD64rm<Mem:(dereferenceable load (s64) from %ir.loc)> t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
; PIC-NEXT:    t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7
; PIC-NEXT:    t11: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t10, t10:1
; PIC-EMPTY:
;
; WIN-LABEL: i64_test:
; WIN:       SelectionDAG has 12 nodes:
; WIN-NEXT:    t0: ch,glue = EntryToken
; WIN-NEXT:    t2: i64,ch = CopyFromReg t0, Register:i64 %0
; WIN-NEXT:    t7: i64,i32,ch = ADD64rm<Mem:(dereferenceable load (s64) from %ir.loc)> t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
; WIN-NEXT:    t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7
; WIN-NEXT:    t11: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t10, t10:1
; WIN-EMPTY:
  %loc = alloca i64
  %j = load i64, i64 * %loc
  %r = add i64 %i, %j
  ret i64 %r
}

define i64 @i32_test(i32 %i) nounwind readnone {
; PIC-LABEL: i32_test:
; PIC:       SelectionDAG has 15 nodes:
; PIC-NEXT:    t0: ch,glue = EntryToken
; PIC-NEXT:    t2: i32,ch = CopyFromReg t0, Register:i32 %0
; PIC-NEXT:    t7: i32,i32,ch = ADD32rm<Mem:(dereferenceable load (s32) from %ir.loc)> t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
; PIC-NEXT:    t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6>
; PIC-NEXT:    t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
; PIC-NEXT:    t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
; PIC-EMPTY:
;
; WIN-LABEL: i32_test:
; WIN:       SelectionDAG has 15 nodes:
; WIN-NEXT:    t0: ch,glue = EntryToken
; WIN-NEXT:    t2: i32,ch = CopyFromReg t0, Register:i32 %0
; WIN-NEXT:    t7: i32,i32,ch = ADD32rm<Mem:(dereferenceable load (s32) from %ir.loc)> t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
; WIN-NEXT:    t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6>
; WIN-NEXT:    t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
; WIN-NEXT:    t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
; WIN-EMPTY:
  %loc = alloca i32
  %j = load i32, i32 * %loc
  %r = add i32 %i, %j
  %ext = zext i32 %r to i64
  ret i64 %ext
}

define i64 @i16_test(i16 %i) nounwind readnone {
; PIC-LABEL: i16_test:
; PIC:       SelectionDAG has 18 nodes:
; PIC-NEXT:    t0: ch,glue = EntryToken
; PIC-NEXT:    t2: i32,ch = CopyFromReg t0, Register:i32 %0
; PIC-NEXT:    t3: i16 = EXTRACT_SUBREG t2, TargetConstant:i32<4>
; PIC-NEXT:    t8: i16,i32,ch = ADD16rm<Mem:(dereferenceable load (s16) from %ir.loc)> t3, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
; PIC-NEXT:    t15: i32 = MOVZX32rr16 t8
; PIC-NEXT:    t9: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t15, TargetConstant:i32<6>
; PIC-NEXT:    t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9
; PIC-NEXT:    t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1
; PIC-EMPTY:
;
; WIN-LABEL: i16_test:
; WIN:       SelectionDAG has 16 nodes:
; WIN-NEXT:    t0: ch,glue = EntryToken
; WIN-NEXT:    t2: i16,ch = CopyFromReg t0, Register:i16 %0
; WIN-NEXT:    t7: i16,i32,ch = ADD16rm<Mem:(dereferenceable load (s16) from %ir.loc)> t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
; WIN-NEXT:    t14: i32 = MOVZX32rr16 t7
; WIN-NEXT:    t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t14, TargetConstant:i32<6>
; WIN-NEXT:    t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
; WIN-NEXT:    t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
; WIN-EMPTY:
  %loc = alloca i16
  %j = load i16, i16 * %loc
  %r = add i16 %i, %j
  %ext = zext i16 %r to i64
  ret i64 %ext
}

define i64 @i8_test(i8 %i) nounwind readnone {
; PIC-LABEL: i8_test:
; PIC:       SelectionDAG has 18 nodes:
; PIC-NEXT:    t0: ch,glue = EntryToken
; PIC-NEXT:    t2: i32,ch = CopyFromReg t0, Register:i32 %0
; PIC-NEXT:    t3: i8 = EXTRACT_SUBREG t2, TargetConstant:i32<1>
; PIC-NEXT:    t8: i8,i32,ch = ADD8rm<Mem:(dereferenceable load (s8) from %ir.loc)> t3, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
; PIC-NEXT:    t15: i32 = MOVZX32rr8 t8
; PIC-NEXT:    t9: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t15, TargetConstant:i32<6>
; PIC-NEXT:    t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9
; PIC-NEXT:    t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1
; PIC-EMPTY:
;
; WIN-LABEL: i8_test:
; WIN:       SelectionDAG has 16 nodes:
; WIN-NEXT:    t0: ch,glue = EntryToken
; WIN-NEXT:    t2: i8,ch = CopyFromReg t0, Register:i8 %0
; WIN-NEXT:    t7: i8,i32,ch = ADD8rm<Mem:(dereferenceable load (s8) from %ir.loc)> t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0
; WIN-NEXT:    t14: i32 = MOVZX32rr8 t7
; WIN-NEXT:    t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t14, TargetConstant:i32<6>
; WIN-NEXT:    t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
; WIN-NEXT:    t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
; WIN-EMPTY:
  %loc = alloca i8
  %j = load i8, i8 * %loc
  %r = add i8 %i, %j
  %ext = zext i8 %r to i64
  ret i64 %ext
}
